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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">GICR_NSACR, Non-secure Access Control Register</h1><p>The GICR_NSACR characteristics are:</p><h2>Purpose</h2>
        <p>Enables Secure software to permit Non-secure software to create SGIs targeting the PE connected to this Redistributor by writing to <a href="AArch64-icc_sgi1r_el1.html">ICC_SGI1R_EL1</a>, <a href="AArch64-icc_asgi1r_el1.html">ICC_ASGI1R_EL1</a> or <a href="AArch64-icc_sgi0r_el1.html">ICC_SGI0R_EL1</a>.</p>

      
        <p>For more information, see <span class="xref">'Forwarding an SGI to a target PE' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069)</span>.</p>
      <h2>Configuration</h2>
        <p>For a description on when a write to <a href="AArch64-icc_sgi0r_el1.html">ICC_SGI0R_EL1</a>, <a href="AArch64-icc_sgi1r_el1.html">ICC_SGI1R_EL1</a> or <a href="AArch64-icc_asgi1r_el1.html">ICC_ASGI1R_EL1</a> is permitted to generate an interrupt, see <span class="xref">'Use of control registers for SGI forwarding' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069)</span>.</p>
      <h2>Attributes</h2>
        <p>GICR_NSACR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="2"><a href="#fieldset_0-31_0">NS_access15</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">NS_access14</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">NS_access13</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">NS_access12</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">NS_access11</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">NS_access10</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">NS_access9</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">NS_access8</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">NS_access7</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">NS_access6</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">NS_access5</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">NS_access4</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">NS_access3</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">NS_access2</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">NS_access1</a></td><td class="lr" colspan="2"><a href="#fieldset_0-31_0">NS_access0</a></td></tr></tbody></table><h4 id="fieldset_0-31_0">NS_access&lt;x&gt;, bits [2x+1:2x], for x = 15 to 0</h4><div class="field">
      <p>Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1, as defined from <a href="ext-gicr_igroupr0.html">GICR_IGROUPR0</a> and <a href="ext-gicr_igrpmodr0.html">GICR_IGRPMODR0</a>. A field is provided for each SGI. The possible values of each 2-bit field are:</p>
    <table class="valuetable"><tr><th>NS_access&lt;x&gt;</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>Non-secure writes are not permitted to generate Secure Group 0 SGIs or Secure Group 1 SGIs.</p>
        </td></tr><tr><td class="bitfield">0b01</td><td>
          <p>Non-secure writes are permitted to generate a Secure Group 0 SGI.</p>
        </td></tr><tr><td class="bitfield">0b10</td><td>
          <p>As <span class="binarynumber">0b01</span>, but additionally Non-secure writes to are permitted to generate a Secure Group 1 SGI.</p>
        </td></tr><tr><td class="bitfield">0b11</td><td><p>Reserved.</p>
<p>If the field is programmed to the reserved value, then the hardware will treat the field as if it has been programmed to an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> choice of the valid values. However, to maintain the principle that as the value increases additional accesses are permitted Arm strongly recommends that implementations treat this value as <span class="binarynumber">0b10</span>. It is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether the value read back is the value programmed or the valid value chosen.</p></td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a GIC reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h2>Accessing GICR_NSACR</h2>
        <p>This register is used when affinity routing is enabled. When affinity routing is not enabled for the Security state of the interrupt, <a href="ext-gicd_nsacrn.html">GICD_NSACR&lt;n&gt;</a> with n=0 provides equivalent functionality.</p>

      
        <p>This register does not support PPIs.</p>
      <h4>GICR_NSACR can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>GIC Redistributor</td><td>SGI_base</td><td><span class="hexnumber">0x0E00</span></td><td>GICR_NSACR</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When GICD_CTLR.DS == 1, accesses to this register are <span class="access_level">RAZ/WI</span>.
          </li><li>When GICD_CTLR.DS == 0 and an access is Secure, accesses to this register are <span class="access_level">RW</span>.
          </li><li>When GICD_CTLR.DS == 0 and an access is Non-secure, accesses to this register are <span class="access_level">RAZ/WI</span>.
          </li><li>When GICD_CTLR.DS == 0, FEAT_RME is implemented and an access is Root, accesses to this register are <span class="access_level">RW</span>.
          </li><li>When GICD_CTLR.DS == 0, FEAT_RME is implemented and an access is Realm, accesses to this register are <span class="access_level">RAZ/WI</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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